Our expertise

SystemVerilog/VHDL RTL design and simulation
Logic and physical synthesis

(Synopsys, Cadence, Vivado)
Static timing analysis, CDC, LEC, Lint
Detailed Verilog modeling of analog circuits and components
Git, SVN, CVS, Cliosoft, Jira, Perforce
FPGA implementation (Xilinx/Altera)

 C/C++/Python modeling at the system and component level Algorithm design and analysis (Matlab/Octave/SciPy/SPW) Magnetic finite-element analysis

Demodulators/Modems: ORAN/QPSK/QAM/ FSK/PSK/OFDM

Clock and symbol recovery: Digital PLL/ phase detectors/analysis/8b10b/character sync
Digital filter design and signal identification
Fixed-point optimization with our own C++ library

Noise shaping: delta-sigma/psychoacoustic
Encryption and encoding
Channel modeling: ISI/fading/interferers/adjacent channel/noise

Deep audio and acoustics expertise

Need to learn more about a specific technology, process node, interface, or methodology? We can provide consulting services and training to your engineering staff, reducing your ramp-up time and potentially eliminating costly silicon revisions. 

Take advantage of our experience by having us take part in your own design reviews.  

We offer our tool expertise as a service, drawing on our years of experience in chip design to benefit you.